• S/N- > 100dbA (approx 5nv/hz).
• THD- <0.15% (<0.1% typical); <1%THD (10Vout, 100K load)
• 20Hz – 20KHz (< -0.5db with IHF 10K/1nf load)
• Output Impedance <100 Ohm
• Can use 6cg7, 6N11,ECC 88, 6DJ8, 6922, 6H1 only

CSS

1. The indicated trace is cut and resistor placed across it to prevent oscillation. Resistor from 1K to 5K is acceptable
2. Connect B+ as shown, or optionally a 1ohm resistor can be connected from that trace to the trace labelled B+. In that case B+ connects to the labelled B+
3. Connect anode as shown to reduce possibility of oscillation. Keep all leads short.
4. Adjustable pot is 2K and can adjust the CCS from 2 to 100ma. Note: higher current requires heat sinking. Recommended to install to chassis with hardware provided and as shown. Note: the back of the IXYS is conductive and must be insulated from the chassis.
5. Be careful: shorting the IXYS CCS will damage the 10S45M. There is no warranty for that.
6. For referemce: the B+ voltage less the anode voltage below the CCS is the voltage available for signal swing. Ie 400V B+ – 200V anode = 200v so +-100v signal.

Super Regulators There are two “Super Regulators” on “The Clock”. One Super Regulator powers the clock circuit, the other power the special unique buffer section. The regulators use very low noise operational amplifiers, offering a noise performance near the limits of what can be achieved without permanently super cooling the circuit in liquid nitrogen. The Super Regulators also uses the lowest noise voltage reference available (LM329), offering 75nV|/Hz noise performance. This ultra low noise voltage reference is used together with a two-stage low pass, which filters the noise from the reference by a factor of 100 at 1Hz and by a factor of 2500 at 10Hz. The combination makes the lowest noise reference possible for the Super Regulators. More crucially, this performance is maintained even at very low frequencies (< 10Hz). It is the very low frequency noise that tends to dominate jitter in a well designed clock and is very hard to control. Unique buffered output Any clock oscillator’s performance is degraded when being asked to directly drive logic inputs, circuit traces and wiring, some oscillators will not even work at all if loaded too much. Fitting high current, high impedance buffers within millimeters after “The Clock” ensures “The Clock” oscillator operates without any significant load at all. The result is a clock where the theoretical performance of “The Clock” oscillator is realised as it operates into a load and with a power supply that is as close to theoretically perfect as can be made. The Output Buffer drives two separate outputs, one a special circuit that emulates the normal clock crystal found in most players and another that offers an output compatible with the less common 4-Pin “canned oscillator” type. The Crystal Emulation output is not designed to source or sink significant currents. The XO type output can drive up to +/-10mA.

“The Power”

Despite being rated at a low 1.2VA output (12V/0.1A), “The Power” uses an oversized 6VA transformer. The transformer is fitted with a special electrostatic screen to ensure lowest noise possible. It uses Full Wave Rectification (not bridge) with two noiseless schottky diodes. It uses chokes filter on the input. It uses a CRCRC power supply filter with 3,000uF total capacitance. It uses a special low noise 12V regulator. The Circuit Design in “The Power” parallels that of a power supply used for a high-end tube preamp, but scaled to the appropriate voltages for “The Clock”.

Transformer Volume Control (TVC) and Linestage

Builders Guide